US 12,148,734 B2
Transistors, memory cells, and arrangements thereof
Sarah Atanasov, Beaverton, OR (US); Abhishek A. Sharma, Hillsboro, OR (US); Bernhard Sell, Portland, OR (US); Chieh-Jen Ku, Portland, OR (US); Elliot Tan, Portland, OR (US); Hui Jae Yoo, Hillsboro, OR (US); Noriyuki Sato, Hillsboro, OR (US); Travis W. Lajoie, Forest Grove, OR (US); Van H. Le, Beaverton, OR (US); and Thoe Michaelos, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 10, 2020, as Appl. No. 17/117,350.
Prior Publication US 2022/0189913 A1, Jun. 16, 2022
Int. Cl. H01L 25/065 (2023.01); H10B 12/00 (2023.01); H10B 10/00 (2023.01); H10B 20/00 (2023.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01); H10B 63/00 (2023.01)
CPC H01L 25/0652 (2013.01) [H10B 12/31 (2023.02); H10B 10/12 (2023.02); H10B 20/27 (2023.02); H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10B 63/34 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a plurality of memory cells distributed in a hexagonally packed arrangement, wherein an individual memory cell of the plurality of memory cells includes an axially symmetric transistor coupled to an axially symmetric capacitor, an axis of the transistor is aligned with an axis of the capacitor, a gate dielectric of the transistor extends around a channel of the transistor and is materially continuous with a dielectric material of the capacitor; and
a materially continuous layer of an electrically conductive material, wherein the materially continuous layer of the electrically conductive material surrounds channels of transistors of a first subset of the plurality of memory cells that are aligned along a first row and channels of transistors of a second subset of the plurality of memory cells that are aligned along a second row.