CPC H01L 24/82 (2013.01) [H01L 2224/82002 (2013.01); H01L 2224/82101 (2013.01); H01L 2224/82106 (2013.01)] | 12 Claims |
1. A method of manufacturing a semiconductor device, comprising:
forming an interconnection structure on a substrate;
forming a first dielectric layer on the interconnection structure;
forming a sacrificial pattern on the first dielectric layer;
forming a redistribution layer (RDL) on the first dielectric layer and the sacrificial pattern; and
removing the sacrificial pattern to form an air cavity within the RDL, wherein a thickness of the RDL is greater than a height of the air cavity.
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