US 12,148,728 B2
Multi-chip integrated fan-out package
Jie Chen, New Taipei (TW); and Hsien-Wei Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 3, 2022, as Appl. No. 17/646,778.
Application 16/586,531 is a division of application No. 16/052,277, filed on Aug. 1, 2018, granted, now 10,515,922, issued on Dec. 24, 2019.
Application 17/646,778 is a continuation of application No. 16/586,531, filed on Sep. 27, 2019, granted, now 11,217,552.
Claims priority of provisional application 62/586,608, filed on Nov. 15, 2017.
Prior Publication US 2022/0130788 A1, Apr. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 21/3105 (2006.01); H01L 23/31 (2006.01)
CPC H01L 24/24 (2013.01) [H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 21/76885 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/82 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/31053 (2013.01); H01L 23/3128 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/18 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/24265 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82005 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first redistribution structure over a first carrier;
forming a conductive pillar over the first redistribution structure;
attaching a first side of a first die to the first redistribution structure adjacent to the conductive pillar, wherein a second side of the first die facing away from the first redistribution structure has die connectors disposed thereon;
forming a molding material over the first redistribution structure, wherein the molding material surrounds the first die and the conductive pillar; and
bonding a first side of a second redistribution structure to first ones of the die connectors and to the conductive pillar, wherein after the bonding, a dielectric layer of the second redistribution structure closest to the molding material is spaced apart from the molding material.