US 12,148,727 B2
Semiconductor device assembly with die support structures
Brandon P. Wirz, Boise, ID (US); and David R. Hembree, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 12, 2021, as Appl. No. 17/174,905.
Application 17/174,905 is a continuation of application No. 15/603,175, filed on May 23, 2017, granted, now 10,923,447.
Prior Publication US 2021/0167030 A1, Jun. 3, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/14 (2013.01) [H01L 24/03 (2013.01); H01L 24/04 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 24/81 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0347 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05023 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/1412 (2013.01); H01L 2224/14517 (2013.01); H01L 2224/16014 (2013.01); H01L 2224/16052 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17051 (2013.01); H01L 2224/17055 (2013.01); H01L 2224/17517 (2013.01); H01L 2224/81139 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81801 (2013.01); H01L 2224/81815 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06575 (2013.01); H01L 2924/3511 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A Semiconductor package comprising a plurality of dies arranged in a stack,
wherein adjacent ones of the plurality of dies are separated by a plurality of interconnects and a plurality of die support structures,
wherein each of the plurality of die support structures includes a stand-off pillar and a stand-oil pad with a first distance between the stand-off pillar and the stand-off pad,
wherein each of the plurality of interconnects includes a conductive pillar, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad, and
wherein the first distance is less than the solder joint thickness,
wherein the stand-off pad of each of the plurality of die support structures extends from a first planar surface of the first semiconductor die by a greater amount than the conductive pad of each of the plurality of interconnects extends from the first planar surface, and
wherein the stand-oft pillar of each of the plurality of die support structures extends front a second planar surface of the second semiconductor die by a greater amount than the conductive pillar of each of the plurality of interconnects extends from the second planar surface.