US 12,148,719 B2
Forming large chips through stitching
Wen Hsin Wei, Hsinchu (TW); Hsien-Pin Hu, Zhubei (TW); Shang-Yun Hou, Jubei (TW); and Weiming Chris Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/869,296.
Application 15/681,513 is a division of application No. 15/006,838, filed on Jan. 26, 2016, granted, now 9,741,669, issued on Aug. 22, 2017.
Application 17/869,296 is a continuation of application No. 16/704,303, filed on Dec. 5, 2019, granted, now 11,444,038.
Application 16/704,303 is a continuation of application No. 15/681,513, filed on Aug. 21, 2017, granted, now 10,515,906, issued on Dec. 24, 2019.
Prior Publication US 2022/0359433 A1, Nov. 10, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/58 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/564 (2013.01) [H01L 21/76808 (2013.01); H01L 21/76816 (2013.01); H01L 23/585 (2013.01); H01L 24/00 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 23/3128 (2013.01); H01L 23/53238 (2013.01); H01L 23/5329 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/14051 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure comprising:
a die comprising:
a first die-edge;
a second die-edge opposite to, and parallel to, the first die-edge;
a first region, a second region, and a third region between the first region and the second region, wherein the first die-edge and the third region have a first spacing, and wherein the second die-edge and the third region have a second spacing substantially equal to the first spacing, the die comprising:
a substrate; and
a conductive line over the substrate, wherein the conductive line comprises:
a first portion in the first region, wherein the first portion comprises a first edge and a second edge parallel to each other, wherein a first middle line in middle of the first edge and the second edge extends in a lengthwise direction of the conductive line;
a second portion in the second region, wherein the second portion comprises a third edge and a fourth edge parallel to each other, wherein a second middle line in middle of the third edge and the fourth edge extends in the lengthwise direction of the conductive line, and wherein the second middle line is parallel to, and is spaced apart from, the first middle line; and
a third portion in the third region, wherein the third portion has an additional lengthwise direction parallel to the first middle line and the second middle line, and the third portion joins to both of the first portion and the second portion.