US 12,148,717 B2
Through wafer trench isolation between transistors in an integrated circuit
Scott Robert Summerfelt, Garland, TX (US); Thomas Dyer Bonifield, Dallas, TX (US); Sreeram Subramanyam Nasum, Bangalore (IN); Peter Smeys, San Jose, CA (US); and Benjamin Stassen Cook, Los Gatos, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jan. 25, 2022, as Appl. No. 17/583,322.
Application 17/583,322 is a division of application No. 16/717,262, filed on Dec. 17, 2019, granted, now 11,251,138.
Claims priority of provisional application 62/783,377, filed on Dec. 21, 2018.
Prior Publication US 2022/0148912 A1, May 12, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/762 (2006.01); H01L 21/78 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/64 (2006.01)
CPC H01L 23/564 (2013.01) [H01L 21/76232 (2013.01); H01L 21/78 (2013.01); H01L 23/293 (2013.01); H01L 23/3121 (2013.01); H01L 23/642 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method comprising:
forming circuit components on a first surface of a wafer, the wafer having a second surface opposite the first surface;
etching a through wafer trench (TWT) through the wafer from the second surface to the first surface;
filling the TWT with a dielectric material;
forming a layer of the dielectric material on the second surface of the wafer and combining with the dielectric material that fills the TWT, in which the layer of the dielectric material has a first thickness extending from a bottom of the TWT and a second thickness extending from the second surface, the first thickness being larger than the second thickness;
removing a portion of the layer of the dielectric material from cut lines on the wafer; and
cutting the wafer along the cut lines to form integrated circuit (IC) dies each including respective portions of the circuit components.