US 12,148,706 B2
Substrate loss reduction for semiconductor devices
Xin-Hua Huang, Xihu Township (TW); Chung-Yi Yu, Hsin-Chu (TW); and Kuei-Ming Chen, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Apr. 18, 2023, as Appl. No. 18/302,197.
Application 17/568,881 is a division of application No. 17/012,490, filed on Sep. 4, 2020, granted, now 11,222,849, issued on Jan. 11, 2022.
Application 18/302,197 is a continuation of application No. 17/568,881, filed on Jan. 5, 2022, granted, now 11,652,058.
Claims priority of provisional application 63/014,841, filed on Apr. 24, 2020.
Prior Publication US 2023/0253334 A1, Aug. 10, 2023
Int. Cl. H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 29/778 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/82 (2013.01); H01L 29/778 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip comprising:
a semiconductor substrate;
a semiconductor layer overlying the semiconductor substrate; and
a semiconductor device between the semiconductor substrate and the semiconductor layer, wherein the semiconductor device comprises a channel region in the semiconductor layer and further comprises a gate electrode and a source/drain electrode on an underside of the semiconductor layer;
wherein the semiconductor substrate has a first sidewall and a second sidewall facing each other, and wherein at least a portion of the semiconductor device is laterally between the first sidewall and the second sidewall.