US 12,148,702 B2
Semiconductor device with transistor local interconnects
Mahbub Rashed, Santa Clara, CA (US); Irene Y. Lin, Los Altos Hills, CA (US); Steven Soss, Cornwall, NY (US); Jeff Kim, San Jose, CA (US); Chinh Nguyen, Austin, TX (US); Marc Tarabbia, Pleasant Valley, NY (US); Scott Johnson, Wappingers Falls, NY (US); Subramani Kengeri, San Jose, CA (US); and Suresh Venkatesan, Danbury, CT (US)
Assigned to GLOBALFOUNDRIES U.S. INC., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Aug. 2, 2022, as Appl. No. 17/879,574.
Application 15/164,114 is a division of application No. 13/324,740, filed on Dec. 13, 2011, granted, now 9,355,910, issued on May 31, 2016.
Application 17/879,574 is a continuation of application No. 17/039,187, filed on Sep. 30, 2020, granted, now 11,444,031.
Application 17/039,187 is a continuation of application No. 16/502,521, filed on Jul. 3, 2019, granted, now 10,833,018, issued on Nov. 10, 2020.
Application 16/502,521 is a continuation of application No. 15/164,114, filed on May 25, 2016, abandoned.
Prior Publication US 2022/0367360 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/535 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 23/532 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 27/118 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/28518 (2013.01); H01L 21/76895 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 23/53238 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 29/0847 (2013.01); H01L 27/11807 (2013.01); H01L 2924/0002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate;
a first, second, third and fourth transistor on the semiconductor substrate, wherein each transistor includes a source, a drain, and a gate, wherein the gate of the first and third transistors extend longitudinally as part of a first linear strip and wherein the gate of the second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from the first linear strip;
a first gate cut isolation separating the gate of the first transistor from the gate of the third transistor;
a second gate cut isolation separating the gate of the second transistor from the gate of the fourth transistor, wherein the first gate cut isolation and the second gate cut isolation are aligned;
a first CB layer forming a local interconnect layer electrically connected to the gate of the first transistor;
a second CB layer forming a local interconnect layer electrically connected to the gate of the second transistor; and
a CA layer forming a local interconnect layer and extending longitudinally between a first end and a second end thereof, wherein the CA layer is electrically connected to the first and second CB layers;
wherein the first CB layer is electrically connected to the gate of the first transistor adjacent the first end of the CA layer and the second CB layer is electrically connected to the gate of the second transistor adjacent the second end of the CA layer,
wherein the first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate, and
wherein the CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.