US 12,148,682 B2
Memory cell in wafer backside
Biswanath Senapati, Mechanicville, NY (US); Seiji Munetoh, Kawasaki (JP); Nicholas Anthony Lanzillo, Wynantskill, NY (US); Lawrence A. Clevenger, Saratoga Springs, NY (US); Geoffrey Burr, Cupertino, CA (US); and Kohji Hosokawa, Ohtsu (JP)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 15, 2021, as Appl. No. 17/551,457.
Prior Publication US 2023/0187314 A1, Jun. 15, 2023
Int. Cl. G11C 13/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01); H10B 63/00 (2023.01)
CPC H01L 23/481 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0038 (2013.01); H01L 21/76898 (2013.01); H01L 23/53209 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H10B 63/80 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a substrate;
a memory cell formed on a backside of the substrate;
the substrate including:
a buried metal structure connected to at least one device formed on a frontside of the substrate via an interconnect; and
a through-silicon-via (TSV) connected to the buried metal structure and the memory cell formed on the backside of the substrate, wherein the interconnect spans from a frontside metal layer on a surface of the frontside of the substrate to the buried metal structure, the buried metal structure spans from the interconnect to the TSV, and the TSV spans from the buried metal structure to a surface of the backside of the substrate.