US 12,148,678 B2
Semiconductor package and manufacturing method thereof
Wen-Wei Shen, Hsinchu (TW); Sung-Hui Huang, Yilan County (TW); Shang-Yun Hou, Hsinchu (TW); and Kuan-Yu Huang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/873,157.
Application 17/873,157 is a continuation of application No. 16/885,304, filed on May 28, 2020, granted, now 11,502,015.
Prior Publication US 2022/0359335 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H01L 21/268 (2006.01); H01L 23/29 (2006.01)
CPC H01L 23/3192 (2013.01) [H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 21/268 (2013.01); H01L 23/293 (2013.01); H01L 2224/16145 (2013.01)] 20 Claims
OG exemplary drawing
 
14. A semiconductor package, comprising:
an interposer comprising a bonding region;
semiconductor dies disposed on the interposer to cover the bonding region;
a first rounded corner structure distributed aside a first corner region of the bonding region; and
an encapsulant laterally encapsulating the semiconductor dies and the first rounded corner structure, wherein the encapsulant and the first rounded corner structure are different in material, wherein a top surface of the first rounded corner structure, backside surfaces of the semiconductor dies and a top surface of the encapsulant are coplanar in a horizontal direction.