US 12,148,676 B2
Embedded chip package and manufacturing method thereof
Xianming Chen, Guangdong (CN); Jindong Feng, Guangdong (CN); Benxia Huang, Guangdong (CN); Lei Feng, Guangdong (CN); and Wenshi Wang, Guangdong (CN)
Assigned to Zhuhai ACCESS Semiconductor Co., Ltd., Guangdong (CN)
Filed by Zhuhai ACCESS Semiconductor Co., Ltd., Guangdong (CN)
Filed on Nov. 14, 2023, as Appl. No. 18/389,264.
Application 18/389,264 is a division of application No. 17/044,087, granted, now 11,854,920, previously published as PCT/CN2020/089735, filed on May 12, 2020.
Claims priority of application No. 202010255623.9 (CN), filed on Apr. 2, 2020.
Prior Publication US 2024/0087972 A1, Mar. 14, 2024
Int. Cl. H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/04 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/36 (2006.01); H01L 23/48 (2006.01); H01L 23/485 (2006.01)
CPC H01L 23/3107 (2013.01) [H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/041 (2013.01); H01L 23/293 (2013.01); H01L 23/36 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 24/96 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method for manufacturing an embedded chip package, the method comprising:
obtaining a chip socket array comprising a frame, wherein the frame is formed therein with a frame via-post passing through a height of the frame;
placing the chip socket array onto an adhesive tape;
placing a chip, with a terminal face of the chip facing downwards, into a cavity of the chip socket array surrounded by the frame;
laminating or coating a first photosensitive polymer dielectric onto the chip and the frame such that the first photosensitive polymer dielectric fully fills a gap between the chip and the frame and covers a back face of the chip and an upper surface of the frame;
exposing and developing the first photosensitive polymer dielectric to form a first pattern which forms a first blind via exposing an end of the frame via-post at the upper surface of the frame and a second blind via revealing the back face of the chip;
removing the adhesive tape, and laminating or coating a second photosensitive polymer dielectric onto the terminal face of the chip and a lower surface of the frame;
exposing and developing the second photosensitive polymer dielectric to form a second pattern which forms a third blind via exposing a terminal of the chip and a fourth blind via exposing an end of the frame via-post at the lower surface of the frame;
applying a metal seed layer onto the first pattern and the second pattern;
applying a photoresist layer onto the metal seed layer, and patterning the photoresist layer to form a third pattern comprising a first wiring layer and a second wiring layer; and
performing Cu electroplating to simultaneously fill the first, second and third patterns to form first, second, third and fourth via-posts and the first and second wiring layers.