US 12,148,675 B2
Power semiconductor package unit of surface mount technology including a plastic film covering a chip
Chung-Hsiung Ho, Kaohsiung (TW); Wei-Ming Hung, Kaohsiung (TW); Wen-Liang Huang, Kaohsiung (TW); Shun-Chi Shen, Kaohsiung (TW); Chien-Chun Wang, Tainan (TW); and Chi-Hsueh Li, Tainan (TW)
Assigned to Panjit International Inc., Kaohsiung (TW)
Filed by Panjit International Inc., Kaohsiung (TW)
Filed on Dec. 7, 2021, as Appl. No. 17/543,872.
Claims priority of provisional application 63/178,675, filed on Apr. 23, 2021.
Prior Publication US 2022/0344228 A1, Oct. 27, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 23/3107 (2013.01) [H01L 21/4814 (2013.01); H01L 21/568 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/29 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/29147 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A power semiconductor package unit of surface mount technology, comprising:
a chip comprising a front side and a back side, wherein the front side and the back side are opposite to each other, and the front side and the back side each have a signal contact, wherein the chip is a power semiconductor chip;
a plastic film layer covering the chip, the plastic film layer comprising a first via and a second via, each of the first via and the second via having inner surfaces, wherein the first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side of the chip, wherein a conductive layer is formed in each of the first via and the second via, and the conductive layer in the second via is electrically connected to the signal contact of the front side of the chip; and
a conducting layer formed on the back side of the chip, the conducting layer electrically connecting the conductive layer in the first via and the signal contact of the back side of the chip, wherein the conducting layer is an electroplated layer;
wherein the conductive layer in the first via and the conductive layer in the second via both protrude from a surface of the plastic film layer and are conductive terminals of the power semiconductor package unit of surface mount technology;
wherein a surface of each of the conductive terminals has a terminal protection laver; a solder mask is formed between the conductive terminals, and the solder mask is attached on the surface of the plastic film laver; and a back side of the conducting layer forms an insulating protective layer.