US 12,148,673 B2
FinFET devices and methods of forming the same
Chih-Hao Wang, Hsinchu County (TW); Jui-Chien Huang, Hsinchu (TW); Kuo-Cheng Ching, Hsinchu County (TW); Chun-Hsiung Lin, Hsinchu County (TW); and Pei-Hsun Wang, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 1, 2023, as Appl. No. 18/362,987.
Application 17/100,942 is a division of application No. 16/172,848, filed on Oct. 28, 2018, granted, now 10,847,426, issued on Nov. 24, 2020.
Application 18/362,987 is a continuation of application No. 17/100,942, filed on Nov. 23, 2020, granted, now 11,837,506.
Prior Publication US 2023/0411218 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01)
CPC H01L 21/823807 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02614 (2013.01); H01L 21/324 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/1054 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A FinFET device, comprising:
a substrate having at least one first fin and an isolation layer covering a lower portion of the at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer; and
a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode,
wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer but separated from the first material layer.