US 12,148,671 B2
Semiconductor devices and methods of manufacturing thereof
Shih-Yao Lin, Hsinchu (TW); Chao-Cheng Chen, Hsinchu (TW); Chih-Han Lin, Hsinchu (TW); Chen-Ping Chen, Hsinchu (TW); Ming-Ching Chang, Hsinchu (TW); Chia-Hao Yu, Hsinchu (TW); and Hsiao Wen Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,943.
Application 18/446,943 is a continuation of application No. 17/376,960, filed on Jul. 15, 2021, granted, now 11,854,899.
Prior Publication US 2024/0014073 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/31144 (2013.01); H01L 21/823418 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/41775 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, comprising:
forming a plurality of fins over a substrate;
forming dummy gates patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates;
forming recesses in the fins by using the patterned dummy gates as a mask;
forming a passivation layer over the fins and in the recesses in the fins;
patterning the passivation layer to leave a remaining passivation layer in some of the recesses in the fins; and
epitaxially forming source and drain regions in the recesses in the fins without the remaining passivation layer.