US 12,148,670 B2
Method for manufacturing fin field effect transistor
Yong Li, Shanghai (CN)
Assigned to Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed by Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed on Mar. 11, 2022, as Appl. No. 17/692,992.
Claims priority of application No. 202110273758.2 (CN), filed on Mar. 15, 2021.
Prior Publication US 2022/0293472 A1, Sep. 15, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/762 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for manufacturing a fin field effect transistor, comprising:
step 1: providing a semiconductor substrate, defining a formation area of fins, and performing a first time etching on the semiconductor substrate to form a top portion of the fins, wherein the top portion is configured to have a first section under a second section, and wherein the second section serves as a channel layer;
step 2: forming sacrificial sidewalls on side surfaces of the second section;
step 3: forming a doped dielectric layer in direct contact with side surfaces of the first section;
step 4: performing a dopant drive process to diffuse dopants of the doped dielectric layer into the first section, wherein the doped first section serves as an anti-punchthrough layer;
step 5: removing the doped dielectric layer and the sacrificial sidewalls;
step 6: performing a second time etching on the semiconductor substrate to form a bottom portion of the fins in a self-aligned manner, wherein each of the fins includes the bottom portion and the top portion; and
step 7: forming a dielectric isolation layer between the fins, wherein an extension of a top surface of the dielectric isolation layer is arranged between a top surface and a bottom surface of the anti-punchthrough layer.