US 12,148,664 B2
Semiconductor device and method having a through substrate via and an interconnect structure
Ming-Fa Chen, Taichung (TW); Tzuan-Horng Liu, Longtan Township (TW); and Chao-Wen Shih, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/874,741.
Application 17/874,741 is a division of application No. 17/012,312, filed on Sep. 4, 2020, granted, now 11,658,069.
Claims priority of provisional application 63/000,404, filed on Mar. 26, 2020.
Prior Publication US 2022/0375793 A1, Nov. 24, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/3065 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 21/76898 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 21/30655 (2013.01); H01L 21/76814 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/8083 (2013.01); H01L 2224/83896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein;
forming a first patterned mask over the first dielectric layer;
performing a first etch process using the first patterned mask as a mask, the first etch process forming a first opening through the first dielectric layer exposing a first portion of the first substrate;
performing a second etch process using the first patterned mask as a mask, the second etch process etching the exposed first portion of the first substrate to form a second opening in the first substrate, the second opening having a same diameter as the first opening;
after forming the second opening in the first substrate, depositing a barrier layer on exposed sidewalls of first dielectric layer in the first opening, sidewalls of the second opening being free of the barrier layer;
forming a liner on the barrier layer in the first opening and on the sidewalls of the first substrate in the second opening;
filling the first opening and the second opening with a conductive material; and
thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first dielectric layer and the first substrate forming a through substrate via.