US 12,148,657 B2
Semiconductor structure and method for forming the same
Chien-Han Chen, Hsinchu (TW); Shih-Yu Chang, Hsinchu (TW); Chien-Chih Chiu, Xinying (TW); Yi-Tang Chen, Hsinchu (TW); and Da-Wei Lin, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 27, 2023, as Appl. No. 18/190,328.
Application 18/190,328 is a continuation of application No. 17/166,539, filed on Feb. 3, 2021, granted, now 11,615,983.
Claims priority of provisional application 63/013,937, filed on Apr. 22, 2020.
Prior Publication US 2024/0332069 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76832 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a via in contact with a conductive line and extending through a first etch stop layer, a first inter-metal dielectric layer, and a second etch stop layer, wherein the second etch stop layer is disposed over the first inter-metal dielectric layer, and the first inter-metal dielectric layer is disposed over the first etch stop layer; and
a trench in contact with the via and extending through an insulating layer and a second inter-metal dielectric layer, wherein the second inter-metal dielectric layer is disposed over the insulating layer which is disposed over the second etch stop layer;
wherein a junction of the via and the trench is aligned with an interface between the second etch stop layer and the insulating layer.