US 12,148,654 B2
Semiconductor structure including a trench having a high aspect ratio formed by etching and its manufacturing method as applied to formation of a capacitor in the semiconductor structure
Yong Lu, Hefei (CN); and Minghung Hsieh, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/595,575
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Mar. 25, 2021, PCT No. PCT/CN2021/083066
§ 371(c)(1), (2) Date Nov. 19, 2021,
PCT Pub. No. WO2021/213129, PCT Pub. Date Oct. 28, 2021.
Claims priority of application No. 202010317800.1 (CN), filed on Apr. 21, 2020.
Prior Publication US 2022/0223468 A1, Jul. 14, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 49/02 (2006.01)
CPC H01L 21/76805 (2013.01) [H01L 21/31111 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76895 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 28/91 (2013.01); H01L 2221/1063 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate and a dielectric layer located on the substrate, the substrate being provided therein with a conductive structure;
etching the dielectric layer to form a first groove;
performing an isotropic etching process on the dielectric layer located at a bottom of the first groove to form a second groove, a maximum width of the second groove being greater than a bottom width of the first groove in a direction parallel with a surface of the substrate;
etching the dielectric layer located at a bottom of the second groove to form a third groove exposing the conductive structure; and
forming a first electrode layer comprising a first part on a side wall of the first groove, a second part on a side wall of the second groove and a third part on a side wall and bottom of the third groove;
forming a capacitor dielectric layer on a surface of the first electrode layer;
forming a second electrode layer on a surface of the capacitor dielectric layer; and,
wherein the first part, the second part and the third part are integrally formed and in sequence along a direction of the first electrode layer facing the substrate, and the third part is in contact with the conductive structure, a sidewall of the second groove is a circular arc-shaped side wall, and the circular arc-shaped side wall is recessed towards a direction away from a center of the second groove.
 
7. A semiconductor structure, comprising:
a substrate being provided therein with a conductive structure; and
a first electrode layer comprising a first part, a second part and a third part in sequence along a direction of the first electrode layer facing the substrate, a maximum width of the second part being greater than a bottom width of the first part in a direction parallel with a surface of the substrate, the third part being in contact with the conductive structure;
a capacitor dielectric layer provided on a surface of the first electrode layer; and
a second electrode layer provided on a surface of the capacitor dielectric layer; and,
wherein the second part has a circular arc-shaped side wall, the first electrode layer and the second electrode layer have circular arc-shaped surfaces which are recessed in a direction away from a center of the second part.