US 12,148,653 B2
Method of manufacturing semiconductor devices
Ru-Gun Liu, Zhubei (TW); Chin-Hsiang Lin, Hsinchu (TW); Chih-Ming Lai, Hsinchu (TW); Wei-Liang Lin, Hsinchu (TW); and Yung-Sung Yen, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 10, 2021, as Appl. No. 17/316,555.
Application 17/316,555 is a continuation of application No. 16/374,150, filed on Apr. 3, 2019, granted, now 11,004,729, issued on May 11, 2021.
Claims priority of provisional application 62/690,829, filed on Jun. 27, 2018.
Prior Publication US 2021/0280455 A1, Sep. 9, 2021
Int. Cl. H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 27/12 (2006.01)
CPC H01L 21/76805 (2013.01) [H01L 21/76814 (2013.01); H01L 21/76877 (2013.01); H01L 27/127 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first underlying layer over a substrate;
forming a second underlying layer over the first underlying layer;
forming a first resist pattern having a first opening over the second underlying layer;
patterning the first and second underlying layers by using the first resist pattern as an etching mask, thereby forming a second opening in the first and second underlying layers;
expanding the second opening in a first axis by directional etching of the second underlying layer to form a first groove in the second underlying layer so that a part of an upper surface of the first underlying layer is exposed around the second opening in the first underlying layer;
forming a second resist pattern including a fourth opening partially overlapping the first groove; and
patterning the second underlying layer by using the second resist pattern as an etching mask to form a first trench in the second underlying layer.