US 12,148,628 B2
Semiconductor device and corresponding method
Roseanne Duca, Ghaxaq (MT); Dario Paci, Vittuone (IT); and Pierpaolo Recanatini, Ornago (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics (MALTA) Ltd, Kirkop (MT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics (MALTA) Ltd, Kirkop (MT)
Filed on Sep. 12, 2022, as Appl. No. 17/942,843.
Application 17/942,843 is a division of application No. 17/108,471, filed on Dec. 1, 2020, granted, now 11,443,958.
Claims priority of application No. 102019000022656 (IT), filed on Dec. 2, 2019.
Prior Publication US 2023/0005755 A1, Jan. 5, 2023
Int. Cl. H01L 21/324 (2006.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01)
CPC H01L 21/324 (2013.01) [H01L 23/16 (2013.01); H01L 23/3107 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method of manufacturing, comprising:
mounting a semiconductor die to a die pad of a leadframe which also includes a set of electrically conductive leads, wherein the semiconductor die has a first surface facing away from the die pad and a second surface opposed to the first surface mounted to the die pad;
forming a containment structure at the first surface of the semiconductor die, the containment structure comprising a peripheral wall configured to define a closed perimeter surrounding a cavity over a selected portion of said first surface of the semiconductor die;
filling the cavity with a stress absorbing material;
electrically coupling the semiconductor die to said electrically conductive leads; and
depositing material for encapsulating the semiconductor die, the containment structure and the stress absorbing material.