US 12,148,627 B2
Method for forming semiconductor memory structure
Hsin-Hung Chou, Taichung (TW); Tsung-Wei Lin, Taichung (TW); and Kao-Tsair Tsai, Taichung (TW)
Assigned to WINBOND ELECTRONICS CORP., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Sep. 21, 2021, as Appl. No. 17/480,757.
Claims priority of application No. 109134581 (TW), filed on Oct. 6, 2020.
Prior Publication US 2022/0108894 A1, Apr. 7, 2022
Int. Cl. H01L 21/3213 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H10B 41/30 (2023.01)
CPC H01L 21/32139 (2013.01) [H01L 21/0274 (2013.01); H01L 21/31138 (2013.01); H10B 41/30 (2023.02); H01L 29/6656 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor memory structure, comprising:
sequentially forming an active layer, a hard mask layer and a core layer over a substrate;
etching the core layer to form a core pattern, wherein the core pattern comprises a first strip, a second strip, and a plurality of supporting features abutting the first strip and the second strip;
forming a spacer layer alongside the core pattern, wherein forming the spacer layer comprises:
forming a conform layer along the core pattern and filling a plurality of openings which are defined by the first strip, the second strip and the plurality of supporting features; and
etching the conform layer;
removing the core pattern;
forming a photoresist pattern above the spacer layer;
etching the hard mask layer using the photoresist pattern and the spacer layer to form a hard mask pattern; and
transferring the hard mask pattern into the active layer to form a gate stack,
wherein the plurality of supporting features extends in a first direction, and the first strip and the second strip extend in a second direction that is substantially perpendicular to the first direction.
 
12. A method for forming a semiconductor memory structure, comprising:
sequentially forming an active layer, a hard mask layer and a core layer over a substrate;
forming a first photoresist pattern and a second photoresist pattern over the core layer, wherein the second photoresist pattern comprises a first strip, a second strip, and a plurality of connecting features extending from the first strip to the second strip;
transferring the first photoresist pattern and the second photoresist into the core pattern to form a first core pattern and a second core pattern respectively, wherein the second core pattern comprises a third strip, a fourth strip, and a plurality of supporting features extending from the third strip to the fourth strip;
forming a pair of first spacers on opposite sides of the first core pattern and a pair of second spacers on opposite sides of the second core pattern, wherein forming the pair of first spacers and the pair of second spacers comprises:
forming a conformal layer along the first and second core patterns to fill a plurality of openings which are defined by the third strip, the fourth trop and the plurality of supporting features;
removing the first core pattern and the second core pattern;
forming a third photoresist pattern over the pair of second spacers; and
etching the hard mask layer and the active layer using the third photoresist pattern, the pair of first spacers, and the pair of second spacers.