US 12,148,622 B2
Semiconductor devices
Yu-Lien Huang, Jhubei (TW); Guan-Ren Wang, Hsinchu (TW); and Ching-Feng Fu, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 26, 2023, as Appl. No. 18/341,332.
Application 17/869,996 is a division of application No. 16/869,861, filed on May 8, 2020, granted, now 11,398,385, issued on Jul. 26, 2022.
Application 18/341,332 is a continuation of application No. 17/869,996, filed on Jul. 21, 2022, granted, now 11,854,814.
Prior Publication US 2023/0352308 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/285 (2006.01); H01L 21/02 (2006.01); H01L 21/48 (2006.01)
CPC H01L 21/28556 (2013.01) [H01L 21/02074 (2013.01); H01L 21/4828 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a gate structure over a substrate;
a source/drain region adjacent the gate structure;
a first inter-layer dielectric over the source/drain region;
a second inter-layer dielectric over the first inter-layer dielectric and the gate structure;
a contact extending through the second inter-layer dielectric and the first inter-layer dielectric to contact the source/drain region, an upper portion of the contact protruding from a top surface of the second inter-layer dielectric; and
a conductive feature on the upper portion of the contact.