US 12,148,620 B2
Tuning threshold voltage through meta stable plasma treatment
Shao-Jyun Wu, New Taipei (TW); Sheng-Liang Pan, Hsinchu (TW); and Huan-Just Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 12, 2023, as Appl. No. 18/316,307.
Application 18/316,307 is a continuation of application No. 17/648,159, filed on Jan. 17, 2022, granted, now 11,688,606.
Application 17/648,159 is a continuation of application No. 16/740,878, filed on Jan. 13, 2020, granted, now 11,239,083, issued on Feb. 1, 2022.
Application 16/740,878 is a continuation of application No. 16/297,970, filed on Mar. 11, 2019, granted, now 10,535,524, issued on Jan. 14, 2020.
Prior Publication US 2023/0282484 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/28 (2006.01); G03F 7/09 (2006.01); G03F 7/16 (2006.01); G03F 7/20 (2006.01); G03F 7/26 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/30 (2006.01); H01L 21/32 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 21/324 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/28185 (2013.01) [G03F 7/091 (2013.01); G03F 7/16 (2013.01); G03F 7/20 (2013.01); G03F 7/26 (2013.01); H01L 21/02252 (2013.01); H01L 21/0234 (2013.01); H01L 21/0276 (2013.01); H01L 21/28088 (2013.01); H01L 21/28158 (2013.01); H01L 21/28176 (2013.01); H01L 21/28211 (2013.01); H01L 21/30 (2013.01); H01L 21/32 (2013.01); H01L 21/3205 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 21/324 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first high-k dielectric layer in a first device region of a wafer;
forming a second high-k dielectric layer in a second device region of the wafer;
depositing a metal layer over the first high-k dielectric layer and the second high-k dielectric layer;
forming an etching mask over the metal layer;
performing a patterning process using the etching mask to remove the metal layer from the first device region, wherein a portion of the metal layer remains in the second device region;
generating a first plasma from a first process gas comprising nitrogen (N2), helium, and hydrogen (H2), wherein the nitrogen and the helium are conducted into a respective tool through a first inlet, and wherein the hydrogen is conducted into the respective tool from a second inlet;
removing the etching mask using the first plasma; and
forming a first conductive feature over the first high-k dielectric layer and a second conductive feature over the metal layer.