US 12,148,617 B2
Structure and method to pattern pitch lines
Chanro Park, Clifton Park, NY (US); Chi-Chun Liu, Altamont, NY (US); Stuart Sieg, Albany, NY (US); Yann Mignot, Slingerlands, NY (US); Koichi Motoyama, Clifton Park, NY (US); and Hsueh-Chung Chen, Cohoes, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Nov. 1, 2021, as Appl. No. 17/453,010.
Prior Publication US 2023/0138978 A1, May 4, 2023
Int. Cl. H01L 21/033 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 21/0337 (2013.01) [H01L 21/32139 (2013.01); H01L 21/0332 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of semiconductor manufacture comprising:
forming a multi-layered hard mask on top of a conductive metal layer;
forming a plurality of first mandrels as a top layer of the multi-layered hard mask;
forming a first spacer around each of the plurality of first mandrels;
removing the plurality of first mandrels;
cutting the first spacer that was located around each of the plurality of first mandrels to form a plurality of second mandrels;
forming a second spacer around each of the plurality of second mandrels;
forming a first self-aligned pattern that includes a plurality of third mandrels, wherein the first self-aligned pattern includes a plurality of third mandrels having a constant width and a plurality of third mandrels having a varied width;
removing the plurality of second mandrels and the second spacer;
etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask;
forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern; and
etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.