US 12,148,575 B2
Integrated component including a capacitor and discrete varistor
Michael W. Kirk, Simpsonville, SC (US); and Marianne Berolini, Greenville, SC (US)
Assigned to KYOCERA AVX Components Corporation, Fountain Inn, SC (US)
Filed by AVX Corporation, Fountain Inn, SC (US)
Filed on Apr. 16, 2020, as Appl. No. 16/850,142.
Claims priority of provisional application 62/838,410, filed on Apr. 25, 2019.
Prior Publication US 2020/0343051 A1, Oct. 29, 2020
Int. Cl. H01G 4/40 (2006.01); H01G 4/12 (2006.01); H01G 4/228 (2006.01); H01G 4/35 (2006.01); H01L 27/06 (2006.01)
CPC H01G 4/40 (2013.01) [H01G 4/12 (2013.01); H01G 4/228 (2013.01); H01G 4/35 (2013.01); H01L 27/0682 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An integrated component comprising:
a multilayer capacitor having a top surface, a bottom surface opposite the top surface, a first end surface, a second end surface opposite the first end surface, a first side surface, and a second side surface opposite the first side surface, the multilayer capacitor comprising a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination, the multilayer capacitor further comprising:
a body comprising a plurality of dielectric layers;
a first plurality of electrode layers disposed within the body and connected with the first active termination;
a second plurality of electrode layers disposed within the body and connected with the second active termination; and
a third plurality of electrode layers connected with the at least one ground termination and capacitively coupled with each of the first plurality of electrode layers and second plurality of electrode layers to form a first capacitor of the pair of capacitors between the first plurality and third plurality of electrode layers and a second capacitor of the pair of capacitors between the second plurality and third plurality of electrode layers;
a discrete varistor comprising a first external varistor termination connected with the first active termination and a second external varistor termination connected with the second active termination of the multilayer capacitor, the discrete varistor having a clamping voltage within a range of about 15 volts to about 30 volts;
a first lead attached to the first active termination and the first external varistor termination;
a second lead attached to the second active termination and the second external varistor termination; and
a third lead attached to the at least one ground termination,
wherein at least one of the first plurality of electrode layers or the second plurality of electrode layers is connected with a respective one of the first active termination or the second active termination along the first side surface, the second side surface, and a respective one of the first end surface or the second end surface,
wherein the third plurality of electrode layers overlap with the first plurality of electrode layers along a first overlapping area, and
wherein the third plurality of electrode layers overlap with the second plurality of electrode layers along a second overlapping area that is different from the first overlapping area such that the first capacitor of the pair of capacitors has a first capacitance and the second capacitor of the pair of capacitors has a second capacitance that is different from the first capacitance.