US 12,148,504 B2
Random data generation circuit and read/write training circuit
Biao Cheng, Hefei (CN); and Tianchen Lu, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by Changxin Memory Technologies, Inc., Anhui (CN)
Filed on Jan. 5, 2023, as Appl. No. 18/093,728.
Application 18/093,728 is a continuation of application No. PCT/CN2022/103573, filed on Jul. 4, 2022.
Claims priority of application No. 202210711838.6 (CN), filed on Jun. 22, 2022.
Prior Publication US 2023/0420005 A1, Dec. 28, 2023
Int. Cl. G11C 7/10 (2006.01); G06F 7/58 (2006.01); G11C 7/22 (2006.01); H03K 19/21 (2006.01)
CPC G11C 7/1036 (2013.01) [G06F 7/588 (2013.01); G11C 7/222 (2013.01); H03K 19/21 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A random data generation circuit, comprising:
a first shift register and a second shift register, configured to receive a same clock signal, wherein the first shift register comprises n output ends Q1 to Qn, the second shift register comprises n output ends Qn+1 to Q2n, each of the output ends outputs 1-bit data in a clock cycle of the clock signal, and n is an integer greater than or equal to 1; and
a parallel-to-serial circuit, coupled to the output ends of the first shift register and the output ends of the second shift register and configured to convert parallel data output by the output ends Q1 to Q2n in one clock cycle into serial data for output,
wherein an initial value of the first shift register is different from an initial value of the second shift register.