| CPC G11C 5/063 (2013.01) [H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02)] | 10 Claims |
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1. A semiconductor memory device comprising:
a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other;
a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction;
a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction;
a first memory pattern disposed between each of the conductive patterns and the first channel pattern;
a second memory pattern disposed between each of the conductive patterns and the second channel pattern;
a first bit line spaced apart from the stack in the vertical direction, connected to one end of the first channel pattern, and extending in a first direction not parallel to the vertical direction; and
a second bit line extending parallel to the first bit line, spaced apart from the first bit line in a second direction not parallel to the first direction, and connected to one end of the second channel pattern,
wherein the channel separation pattern extends in the first direction to be parallel to the first bit line and the second bit line.
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