	US 12,148,499 B1
	Test system for dynamic random access memory module of AMD system
Wei-Guo Zhao, Shanghai (CN)
Assigned to SQ TECHNOLOGY (SHANGHAI) CORPORATION, Shanghai (CN); and INVENTEC CORPORATION, Taipei (TW)
Filed by SQ TECHNOLOGY (SHANGHAI) CORPORATION, Shanghai (CN); and INVENTEC CORPORATION, Taipei (TW)
Filed on Jun. 19, 2023, as Appl. No. 18/211,529.
Int. Cl. G11C 29/56 (2006.01)

CPC G11C 29/56 (2013.01) [G11C 2029/5602 (2013.01)]

4 Claims

1. A test system for a DRAM of an AMD system, configured to verify information write and read functions of an EEPROM comprised in at least one DRAM, the test system comprising:

at least one memory module slot configured for insertion of the at least one DRAM; and

a BMC, the BMC being electrically coupled to the at least one memory module slot through at least one I²C bus;

wherein the BMC accesses the at least one DRAM through the at least one I²C bus, and writes test data to and reads the test data from the EEPROM;

wherein the test system turns off a sensor of the BMC through an operating system before the BMC accesses the at least one DRAM through the at least one I²C bus and writes the test data to the EEPROM, and the test system turns on the sensor of the BMC after verifying the information write and read functions of the EEPROM.