US 12,148,494 B2
Semiconductor memory devices and methods of operating semiconductor memory devices
Kiheung Kim, Suwon-si (KR); Sanguhn Cha, Suwon-si (KR); Junhyung Kim, Suwon-si (KR); Sungchul Park, Seoul (KR); Hyojin Jung, Hwaseong-si (KR); and Kyung-Soo Ha, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 28, 2023, as Appl. No. 18/115,132.
Application 18/115,132 is a continuation of application No. 17/245,075, filed on Apr. 30, 2021, granted, now 11,626,181.
Claims priority of application No. 10-2020-0122514 (KR), filed on Sep. 22, 2020.
Prior Publication US 2023/0207040 A1, Jun. 29, 2023
Int. Cl. G11C 29/42 (2006.01); G11C 11/406 (2006.01); G11C 29/20 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 11/40615 (2013.01); G11C 29/20 (2013.01); G11C 29/44 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of memory cells arranged into a plurality of memory cell rows, each of the plurality of memory cell rows storing a codeword;
a scrubbing control circuit configured to perform a scrubbing operation on the plurality of memory cells;
an error correction code (ECC) circuit configured to read the codeword from at least one of the plurality of memory cell rows and perform an error detection operation on the codeword; and
a control logic circuit configured to control the ECC circuit to perform a writeback operation or not to perform the writeback operation on the codeword according to the error detection operation performed by the ECC circuit,
wherein the ECC circuit is configured to generate an error generation signal in the error detection operation based on detecting at least one error bit in the codeword, and
wherein the control logic circuit is configured to count a number of error occurrences of the codeword based on the error generation signal, and control the ECC circuit to perform the writeback operation or not perform the writeback operation based on comparing the number of error occurrences of the codeword with a reference value.