US 12,148,493 B2
Memory controller with read error handling
Boxuan Cheng, Wuhan (CN); Wei Tao, Wuhan (CN); Weizhen Kong, Wuhan (CN); and Jian Cao, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Nov. 4, 2022, as Appl. No. 17/981,298.
Application 17/981,298 is a continuation of application No. 17/352,246, filed on Jun. 18, 2021, granted, now 11,521,701.
Application 17/352,246 is a continuation of application No. PCT/CN2021/083886, filed on Mar. 30, 2021.
Prior Publication US 2023/0055737 A1, Feb. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/42 (2006.01); H03M 13/11 (2006.01)
CPC G11C 29/42 (2013.01) [H03M 13/1108 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for handling a read error on a block of a memory device, comprising:
in response to a read failure indicating that each of at least one error handling mechanism, applied after the read error on the block, fails to read data stored in the block;
including the block in a test queue configured for the block waiting to be tested by a memory test;
marking the block with the read error as a temporary bad block; and
triggering to perform the memory test on the block, the memory test being configured to determine whether the block with the read error malfunctions, and the memory test being performed when no task having a priority higher than the memory test to determine whether the block in the test queue is a bad block.