US 12,148,492 B2
Semiconductor device and semiconductor system for detecting an error occurred in a parity
Yeong Han Jeong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Sep. 9, 2022, as Appl. No. 17/941,773.
Claims priority of application No. 10-2022-0028391 (KR), filed on Mar. 4, 2022.
Prior Publication US 2023/0282300 A1, Sep. 7, 2023
Int. Cl. G11C 16/06 (2006.01); G11C 29/18 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/18 (2013.01); G11C 29/44 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor system comprising:
a controller configured to:
output parity information comprising an expected value at which an error correction code (ECC) encoding operation has been performed on an address in a test mode of a semiconductor device; and
receive failure information; and
the semiconductor device configured to:
store an internal parity generated by performing the ECC encoding operation on the address that is input in a normal mode of the semiconductor device; and
output the failure information generated by comparing the parity information and an output parity generated from the internal parity that is stored in the semiconductor device in the test mode, and
wherein the semiconductor device comprises:
an error correction circuit configured to generate the internal parity by performing the ECC encoding operation on the address when an error occurs in internal data output by the address in the normal mode;
a parity storage circuit configured to store the internal parity in the normal mode and to output, as the output parity, the internal parity that is stored in the semiconductor device after a start of a bootup operation in the test mode;
a comparison circuit configured to generate a comparison signal by comparing the output parity and the parity information; and
an output circuit configured to output the comparison signal as the failure information when a test mode signal is enabled.