US 12,148,490 B1
At-speed synchronous write-through operation for testing two-port memory
Harold Pilo, Underhill, VT (US); and Anurag Garg, Cupertino, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Mar. 9, 2023, as Appl. No. 18/119,738.
Int. Cl. G11C 29/00 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 29/12 (2006.01); G11C 29/38 (2006.01)
CPC G11C 29/38 (2013.01) [G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/12015 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for testing memory, comprising:
receiving a synchronous write through (SWT) mode signal that indicates one of a functional mode of operation of the memory and a testing mode of operation of the memory, wherein the testing mode triggers bypassing of one or more read operations from bit cells of the memory identified by read address signals;
switching between the functional mode of operation and the testing mode of operation in dependence on the received SWT mode signal; and
when the memory is in the testing mode of operation, sense amplifiers of the memory (i) receiving test data obtained from the read address signals to represent a test state, (ii) providing the read address signals as sense amplifier outputs and (iii) being disabled from receiving read bitline signals from the bit cells.