US 12,148,489 B2
Early detection of programming failure for non-volatile memory
Yi Song, San Jose, CA (US); Sarath Puthenthermadam, San Jose, CA (US); and Jiahui Yuan, Fremont, CA (US)
Assigned to SanDisk Technologies LLC, Austin, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jul. 26, 2022, as Appl. No. 17/874,014.
Prior Publication US 2024/0038315 A1, Feb. 1, 2024
Int. Cl. G11C 29/12 (2006.01); G11C 11/408 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01)
CPC G11C 29/12005 (2013.01) [G11C 11/4085 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3454 (2013.01); G11C 16/0483 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a block comprising a word line coupled to a plurality of memory cells; and
a control circuit coupled to the word line, the control circuit configured to program the plurality of memory cells by:
applying program pulses to the word line in a plurality of program loops;
determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state;
first comparing the first count to a corresponding first lower limit and a corresponding first upper limit;
determining whether programming the plurality of memory cells has failed based on a result of the first comparing step; and
determining that programming the plurality of memory cells has failed if the first count is less than the corresponding first lower limit or greater than the corresponding first upper limit.