US 12,148,488 B2
Memory system and memory operation
Midori Aizawa, Kanagawa (JP); Masami Kuroda, Kanagawa (JP); and Haruko Takahashi, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/005,046
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed May 20, 2021, PCT No. PCT/JP2021/019164
§ 371(c)(1), (2) Date Jan. 10, 2023,
PCT Pub. No. WO2022/018950, PCT Pub. Date Jan. 27, 2022.
Claims priority of application No. 2020-124039 (JP), filed on Jul. 20, 2020.
Prior Publication US 2023/0260587 A1, Aug. 17, 2023
Int. Cl. G11C 29/10 (2006.01); G06F 11/22 (2006.01)
CPC G11C 29/10 (2013.01) [G06F 11/2215 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a bit line selector;
a soft error generator configured to generate one of write data or read data based on a probability error and a specific number; and
a writing controller configured to output, at a specific timing, the write data to the bit line selector, wherein the bit line selector is configured to store the write data in a specific address of a memory based on a specific voltage.