US 12,148,487 B2
High-density and high-voltage-tolerable pure core memory cell
Ku-Feng Lin, New Taipei (TW); Perng-Fei Yuh, Walnut Creek, CA (US); and Meng-Sheng Chang, Chu-bei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 28, 2022, as Appl. No. 17/587,242.
Claims priority of provisional application 63/230,619, filed on Aug. 6, 2021.
Prior Publication US 2023/0037696 A1, Feb. 9, 2023
Int. Cl. G11C 17/16 (2006.01)
CPC G11C 17/16 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a first storage element coupled to a first bit line;
a first transistor having a first source/drain connected to the first storage element and a second source/drain connected to a center node;
a second storage element coupled to a second bit line;
a second transistor having a first source/drain connected to the second storage element and a second source/drain connected to the center node; and
a third transistor coupled between the center node and a reference node.