US 12,148,486 B2
Read voltage adjustment method, memory storage device and memory control circuit unit
Hsiao-Yi Lin, Yilan County (TW); Shih-Jia Zeng, Hsinchu (TW); Chen Yang Tang, Taoyuan (TW); Shi-Chieh Hsu, Taichung (TW); and Wei Lin, Taipei (TW)
Assigned to PHISON ELECTRONICS CORP., Miaoli (TW)
Filed by PHISON ELECTRONICS CORP., Miaoli (TW)
Filed on Mar. 10, 2023, as Appl. No. 18/181,546.
Claims priority of application No. 112103678 (TW), filed on Feb. 2, 2023.
Prior Publication US 2024/0265983 A1, Aug. 8, 2024
Int. Cl. G11C 16/00 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A read voltage adjustment method, configured for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the read voltage adjustment method comprises:
sending a write command sequence, wherein the write command sequence instructs to program a plurality of first memory cells in the plurality of memory cells;
sending a first read command sequence, wherein the first read command sequence instructs to read the programmed plurality of first memory cells using a first read voltage level to obtain first count information;
obtaining first compensation information corresponding to the first read voltage level, and the first compensation information reflects a deviation in evenly programming the plurality of first memory cells to a plurality of states; and
adjusting the first read voltage level according to the first count information, the first compensation information, and default count information corresponding to the first read voltage level.