US 12,148,485 B2
Memory device and operating method of the memory device including detecting erase cell disturbance during programming
Soo Yeol Chai, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 22, 2022, as Appl. No. 17/871,251.
Claims priority of application No. 10-2022-0009937 (KR), filed on Jan. 24, 2022.
Prior Publication US 2023/0238065 A1, Jul. 27, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells;
a peripheral circuit configured to perform a plurality of program loops on selected memory cells among the plurality of memory cells, each of the plurality of program loops including a program pulse application operation and a program verify operation; and
control logic configured to control the peripheral circuit to suspend an nth program loop (n is a natural number equal to or greater than 1) among the plurality of program loops in response to a suspend command received during the nth program loop, and to resume the nth program loop with a negative verify operation after performing a recovery pulse application operation, in response to a resume command,
wherein in the negative verify operation, a negative voltage having a voltage lower than a verify voltage is applied to a selected word line connected to the selected memory cells at the time of reception of the resume command.