US 12,148,478 B2
Erase method for non-volatile memory with multiple tiers
Xiang Yang, Santa Clara, CA (US); Masaaki Higashitani, Cupertino, CA (US); Abhijith Prakash, Milpitas, CA (US); and Dengtao Zhao, Los Gatos, CA (US)
Assigned to SanDisk Technologies LLC, Austin, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Sep. 26, 2022, as Appl. No. 17/952,846.
Prior Publication US 2024/0105265 A1, Mar. 28, 2024
Int. Cl. G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); H01L 25/065 (2023.01)
CPC G11C 16/14 (2013.01) [G11C 16/0483 (2013.01); G11C 16/3445 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06562 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
a plurality of non-volatile memory cells divided into three or more tiers by a joint region between each pair of neighboring tiers, the three or more tiers comprise outer tiers and one or more inner tiers, each tier of the three or more tiers comprises multiple consecutively connected non-volatile memory cells with no intervening joint region; and
a control circuit connected to the non-volatile memory cells, the control circuit is configured to concurrently erase the non-volatile memory cells in the three or more tiers by applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than a voltage bias applied to control gates of non-volatile memory cells in the one or more inner tiers such that for each joint region between neighboring tiers control gates of all and multiple non-volatile memory cells on a first side of the respective joint region receive a different voltage bias than control gates of all and multiple non-volatile memory cells on a second side of the respective joint region to cause erasing on both sides of the respective joint region.