US 12,148,477 B2
Memory system having semiconductor memory device that performs verify operations using various verify voltages
Masanobu Shirakawa, Chigasaki Kanagawa (JP); Kenta Yasufuku, Yokohama Kanagawa (JP); and Akira Yamaga, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 13, 2023, as Appl. No. 18/466,344.
Application 18/466,344 is a continuation of application No. 17/852,683, filed on Jun. 29, 2022, granted, now 11,804,267.
Application 17/852,683 is a continuation of application No. 17/196,140, filed on Mar. 9, 2021, granted, now 11,410,732, issued on Aug. 9, 2022.
Application 17/196,140 is a continuation of application No. 16/791,607, filed on Feb. 14, 2020, granted, now 10,978,157, issued on Apr. 13, 2021.
Application 16/791,607 is a continuation of application No. 16/354,866, filed on Mar. 15, 2019, granted, now 10,600,485, issued on Mar. 24, 2020.
Application 16/354,866 is a continuation of application No. 15/876,713, filed on Jan. 22, 2018, granted, now 10,276,243, issued on Apr. 30, 2019.
Application 15/876,713 is a continuation of application No. 15/588,560, filed on May 5, 2017, granted, now 9,911,498, issued on Mar. 6, 2018.
Application 15/588,560 is a continuation of application No. 15/174,527, filed on Jun. 6, 2016, granted, now 9,721,666, issued on Aug. 1, 2017.
Claims priority of application No. 2015-179942 (JP), filed on Sep. 11, 2015.
Prior Publication US 2023/0420052 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/34 (2013.01); G11C 16/3427 (2013.01); G11C 16/3459 (2013.01); G11C 11/5642 (2013.01); G11C 2211/5641 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory device including a plurality of memory cells and a word line, the plurality of memory cells corresponding to a first page, the plurality of memory cells comprising first, second, third, and fourth memory cells, the word line being electrically connected to gates of the first, second, third, and fourth memory cells; and
a controller configured to issue a first write command and a second write command to the semiconductor memory device, wherein
the semiconductor memory device is configured to:
execute, in response to the issued first write command, a first program operation on the first page and a first verify operation on the first page using a first verify condition, and
execute, in response to the issued second write command,
a second program operation selectively on a first subset of the first page, the first subset corresponding to the first and second memory cells and not to the third and fourth memory cells, and a second verify operation selectively on the first subset of the first page using a second verify condition when the second write command corresponds to the first subset of the first page, and
the second program operation selectively on a second subset of the first page, the second subset corresponding to the third and fourth memory cells and not to the first and second memory cells, and a third verify operation selectively on the second subset of the first page using a third verify condition when the second write command corresponds to the second subset of the first page.