US 12,148,472 B2
Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
Yuniarto Widjaja, Cupertino, CA (US)
Assigned to Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed by Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed on Jun. 27, 2023, as Appl. No. 18/214,714.
Application 14/738,349 is a division of application No. 13/244,812, filed on Sep. 26, 2011, granted, now 9,087,580, issued on Jul. 21, 2015.
Application 18/214,714 is a continuation of application No. 17/693,751, filed on Mar. 14, 2022, granted, now 11,727,987.
Application 17/693,751 is a continuation of application No. 17/107,904, filed on Nov. 30, 2020, granted, now 11,295,813, issued on Apr. 5, 2022.
Application 17/107,904 is a continuation of application No. 16/407,614, filed on May 9, 2019, granted, now 10,867,676, issued on Dec. 15, 2020.
Application 16/407,614 is a continuation of application No. 16/017,249, filed on Jun. 25, 2018, granted, now 10,340,006, issued on Jul. 2, 2019.
Application 16/017,249 is a continuation of application No. 15/724,651, filed on Oct. 4, 2017, granted, now 10,032,514, issued on Jul. 24, 2018.
Application 15/724,651 is a continuation of application No. 15/292,098, filed on Oct. 12, 2016, granted, now 9,812,203, issued on Nov. 7, 2017.
Application 15/292,098 is a continuation of application No. 14/738,349, filed on Jun. 12, 2015, granted, now 9,490,012, issued on Nov. 8, 2016.
Application 13/244,812 is a continuation of application No. 12/545,623, filed on Aug. 21, 2009, granted, now 8,159,868, issued on Apr. 17, 2012.
Claims priority of provisional application 61/091,071, filed on Aug. 22, 2008.
Prior Publication US 2023/0343392 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 14/00 (2006.01); G06F 3/06 (2006.01); G11C 11/14 (2006.01); G11C 11/402 (2006.01); G11C 11/404 (2006.01); G11C 11/4067 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01); H10B 12/10 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC G11C 14/0045 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0647 (2013.01); G06F 3/0685 (2013.01); G11C 11/14 (2013.01); G11C 11/4026 (2013.01); G11C 11/404 (2013.01); G11C 11/4067 (2013.01); G11C 11/5678 (2013.01); G11C 11/5685 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0033 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H01L 27/1203 (2013.01); H01L 29/7841 (2013.01); H10B 12/00 (2023.02); H10B 12/10 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 63/00 (2023.02); H10B 63/32 (2023.02); H10B 63/80 (2023.02); H10N 70/231 (2023.02); H10N 70/235 (2023.02); H10N 70/24 (2023.02); H10N 70/245 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/882 (2023.02); H10N 70/8833 (2023.02); H10N 70/8836 (2023.02); G11C 2013/0045 (2013.01); G11C 2013/0078 (2013.01); G11C 2211/4016 (2013.01); G11C 2211/5643 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); H10N 70/8828 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
a substrate;
a transistor comprising a source region, a first floating body region, a drain region, and a gate;
a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region, wherein:
one of said cathode region and said anode region comprises said substrate,
a state of said memory cell is stored in said first floating body region,
said first floating body region and said second floating body region are common,
said silicon controlled rectifier device maintains a state of said memory cell, and
said transistor is usable to access said memory cell; and
a nonvolatile memory comprising a resistance change element configured to store data stored in said first floating body region upon transfer to said nonvolatile memory;
wherein when said first floating body region has a first charge level, said nonvolatile memory is configured to a first resistivity level upon said transfer to said nonvolatile memory;
wherein when said first floating body region has a second charge level, said nonvolatile memory is configured to a second resistivity level upon said transfer to said nonvolatile memory; and
wherein said buried layer region is commonly connected to at least two of said memory cells.