US 12,148,471 B2
Reconfigurable computational memory device, operation method of the reconfigurable computational memory device and semiconductor die including the reconfigurable computational memory device
Yun-Feng Kao, New Taipei (TW); and Katherine H Chiang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 22, 2022, as Appl. No. 17/892,130.
Prior Publication US 2024/0062817 A1, Feb. 22, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0038 (2013.01); G11C 13/004 (2013.01); G11C 2013/0054 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
computational memory cells, each configured to have a changeable logic function, and respectively comprising:
a field effect transistor, with a changeable threshold voltage, and defined at an intersection of a channel strip and a gate line, wherein one of the computational memory cells is assigned with a first logic function as the field effect transistor in the one of the computational memory cells is programmed to have a low threshold voltage, and assigned with a second logic function as the field effect transistor in the one of the computational memory cells is programmed to have a high threshold voltage; and
resistive storage devices, separately disposed on a local interconnection line coupled to a source/drain terminal of the field effect transistor, wherein inputs for one of the computational memory cells are provided as resistance states of the resistive storage devices in the one of the computational memory cells, and a current passing through a conduction channel of the field effect transistor in the one of the computational memory cells is an output for the one of the computational memory cells.