US 12,148,470 B2
Driver circuit for phase-change memory cells and method of driving phase-change memory cells
Agatino Massimo Maccarrone, Regalbuto (IT); Antonino Conte, Tremestieri Etneo (IT); Francesco Tomaiuolo, Acireale (IT); Michelangelo Pisasale, Catania (IT); and Marco Ruta, Catania (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jul. 22, 2022, as Appl. No. 17/814,442.
Claims priority of application No. 102021000019574 (IT), filed on Jul. 23, 2021.
Prior Publication US 2023/0021601 A1, Jan. 26, 2023
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a plurality of memory cells, wherein each memory cell in the plurality of memory cells includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal;
a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors in the plurality of memory cells, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses; and
at least one current generator circuit configured to inject a compensation current for the programming currents into the common control node in response to the current-modulating transistors injecting the programming currents into the respective phase-change memory storage elements.