US 12,148,469 B2
Method for manufacturing memory system including a storage device
Tadashi Miyakawa, Yokohama Kanagawa (JP); and Katsuhiko Hoya, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Feb. 28, 2022, as Appl. No. 17/682,770.
Claims priority of application No. 2021-152118 (JP), filed on Sep. 17, 2021.
Prior Publication US 2023/0106886 A1, Apr. 6, 2023
Int. Cl. H10N 50/01 (2023.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); H01L 27/10 (2006.01); H10B 61/00 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC G11C 13/0069 (2013.01) [G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01); H01L 27/101 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a memory system including memory cells with a variable resistance element and a switching element connected between a first wire and second wire, the method comprising:
forming variable resistance elements in the memory system in a low resistance state or a high resistance state; and
bringing each of the variable resistance elements into the low resistance state before performing either of a read operation or a write operation by performing an external initialization process that is different from the read operation and the write operation.