US 12,148,468 B2
Semiconductor memory device and control device for semiconductor memory device
Hiroshi Yoshida, Miyagi (JP); Toshimasa Namekawa, Miyagi (JP); Satoru Araki, Miyagi (JP); Etsuo Fukuda, Miyagi (JP); and Tetsuo Endoh, Miyagi (JP)
Assigned to POWER SPIN INC., Sendai (JP)
Filed by POWER SPIN INC., Miyagi (JP)
Filed on Nov. 17, 2022, as Appl. No. 18/056,341.
Claims priority of application No. 2021-188194 (JP), filed on Nov. 18, 2021.
Prior Publication US 2023/0154532 A1, May 18, 2023
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/0033 (2013.01); G11C 2013/0054 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch;
a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element; and
a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.