US 12,148,467 B2
Decoding for a memory device
Paolo Fantini, Vimercate (IT); Lorenzo Fratin, Buccinasco (IT); and Fabio Pellizzer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 10, 2022, as Appl. No. 17/885,136.
Application 17/885,136 is a continuation of application No. 17/117,953, filed on Dec. 10, 2020, granted, now 11,423,981.
Prior Publication US 2023/0032006 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC G11C 13/0023 (2013.01) [G11C 13/003 (2013.01); H10B 63/84 (2023.02); H10N 70/011 (2023.02); H10N 70/882 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array, wherein a die of the memory array extends in a first direction and a second direction, the memory array comprising:
a memory cell;
an access line coupled with the memory cell; and
a decoder coupled with the access line and configured to bias the access line to one or more voltages, the decoder comprising:
a first n-type transistor coupled with a source node and the access line and positioned in a layer between the memory cell and logic circuits; and
a second n-type transistor coupled with a ground node and the access line and positioned within the layer, wherein the first n-type transistor and the second n-type transistor are vertical transistors extending in a third direction orthogonal to the first direction and the second direction.