US 12,148,464 B2
Current leakage management controller for reading from memory cells
Michael Tsivyan, Campbell, CA (US); Shidong Zhou, Milpitas, CA (US); Karthy Rajasekharan, Austin, TX (US); Weiguang Lu, San Jose, CA (US); Jing Jing Chen, San Jose, CA (US); and Mehul Vashi, San Jose, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Jul. 26, 2021, as Appl. No. 17/385,313.
Prior Publication US 2023/0023614 A1, Jan. 26, 2023
Int. Cl. G11C 11/419 (2006.01); G11C 11/418 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01); H10B 10/12 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first sensing circuit coupled to a first data line and configured to sense a level of current leakage or a memory cell state on the first data line;
a first keeper circuit coupled to the first data line and configured to drive the first data line by a voltage supply through a biased transistor;
a first leakage latch coupled to receive and latch a state of a signal output from the first sensing circuit;
a second sensing circuit coupled to a second data line and configured to sense a level of current leakage or a memory cell state on the second data line;
a second keeper circuit coupled to the second data line and configured to drive the second data line by a voltage supply through a biased transistor;
a second leakage latch coupled to receive and latch a state of a signal output from the second sensing circuit; and
a first control circuit coupled to outputs of the first leakage latch and the second leakage latch and coupled to receive the outputs of the first sensing circuit and the second sensing circuit, wherein the first control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of signals output from the first leakage latch and the second leakage latch.