US 12,148,461 B2
Signal sampling circuit and semiconductor memory device
Zequn Huang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 21, 2022, as Appl. No. 17/949,257.
Application 17/949,257 is a continuation of application No. PCT/CN2022/089853, filed on Apr. 28, 2022.
Claims priority of application No. 202210292978.4 (CN), filed on Mar. 23, 2022.
Prior Publication US 2023/0013811 A1, Jan. 19, 2023
Int. Cl. G11C 11/4076 (2006.01); G06F 1/04 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/12 (2006.01); G11C 8/18 (2006.01); G11C 11/4063 (2006.01); G11C 11/4093 (2006.01); H03K 3/037 (2006.01); H03K 5/135 (2006.01); H03K 19/20 (2006.01); G11C 8/06 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 1/04 (2013.01); G11C 7/10 (2013.01); G11C 7/1087 (2013.01); G11C 7/109 (2013.01); G11C 7/1093 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01); G11C 8/18 (2013.01); G11C 11/4063 (2013.01); G11C 11/4093 (2013.01); H03K 3/037 (2013.01); H03K 5/135 (2013.01); H03K 19/20 (2013.01); G11C 8/06 (2013.01); G11C 11/408 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal sampling circuit, comprising a signal input circuit, a mode selection circuit, a first clock processing circuit, a second clock processing circuit and a command decoding circuit, wherein
the signal input circuit is configured to determine a to-be-processed command signal and a to-be-processed chip select signal according to a first clock signal, a first chip select signal and a first command address signal, a clock cycle of the first clock signal being twice a preset clock cycle,
wherein the mode selection circuit is configured to perform, in response to a mode selection signal indicating a target mode, selection processing on the first clock signal and the to-be-processed chip select signal according to the mode selection signal, to obtain a target mode clock signal and a target mode chip select signal,
wherein the first clock processing circuit is configured to perform, when the first chip select signal includes a pulse with a pulse width of the preset clock cycle, sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a first chip select clock signal,
wherein the second clock processing circuit is configured to perform, when the first chip select signal includes a pulse with a pulse width that is twice the preset clock cycle, or the first chip select signal includes two pulses, each with a pulse width of the preset clock cycle, sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a second chip select clock signal, and
wherein the command decoding circuit is configured to perform decoding and sampling on the to-be-processed command signal according to the to-be-processed chip select signal and the first chip select clock signal, to obtain a target command signal; or, perform decoding and sampling on the to-be-processed command signal according to the to-be-processed chip select signal and the second chip select clock signal, to obtain a target command signal.