US 12,148,459 B2
Cross-point array IHOLD read margin improvement
Ward Parkinson, Boise, ID (US); James O'Toole, Boise, ID (US); Thomas Trent, Tucson, AZ (US); Nathan Franklin, Belmont, CA (US); Michael Grobis, Campbell, CA (US); James W. Reiner, Palo Alto, CA (US); Hans Jurgen Richter, Palo Alto, CA (US); and Michael Nicolas Albert Tran, San Jose, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Feb. 22, 2022, as Appl. No. 17/677,666.
Prior Publication US 2023/0267981 A1, Aug. 24, 2023
Int. Cl. G11C 11/16 (2006.01); G11C 13/00 (2006.01); H10N 50/10 (2023.01); H10N 70/20 (2023.01)
CPC G11C 11/1673 (2013.01) [G11C 11/161 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); G11C 13/0004 (2013.01); G11C 13/0028 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H10N 50/10 (2023.02); H10N 70/20 (2023.02); G11C 2013/0045 (2013.01); G11C 2013/0057 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/72 (2013.01); G11C 2213/76 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a cross-point memory array comprising a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of programmable resistance memory cells, each respective memory cell connected between one of the first conductive lines and one of the second conductive lines, wherein each memory cell comprises a programmable resistance memory element and a two terminal selector connected in series with the memory element;
one or more current sources configured to generate a read current and a write current;
decode and drive circuitry configured to select one of the first conductive lines among the plurality of first conductive lines, the decode and drive circuitry comprising a drive transistor configured to receive the read current and to drive the read current to the selected first conductive line and to receive the write current and to drive the write current to the selected first conductive line; and
a control circuit in communication with the one or more current sources, the decode and drive circuitry and the cross-point memory array, the control circuit configured to:
apply a first overdrive voltage to the drive transistor to cause the drive transistor to drive the read current to the selected first conductive line connected to a selected memory cell;
test a condition of the selected memory cell in response to the read current passing through the selected memory cell while the two terminal selector of the selected memory cell is on; and
apply a second overdrive voltage to the drive transistor to cause the drive transistor to drive the write current to the selected first conductive line to program the selected memory cell to a target state, wherein the first overdrive voltage has a lower magnitude than the second overdrive voltage.