| CPC G09G 3/3677 (2013.01) [G09G 3/3266 (2013.01); G09G 3/3674 (2013.01); G11C 19/28 (2013.01); G02F 1/1345 (2013.01); G02F 1/13454 (2013.01); G09G 3/32 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2330/06 (2013.01)] | 20 Claims |
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1. A display substrate, comprising:
a base substrate and a plurality of shift register units disposed on the base substrate,
wherein the plurality of shift register units are arranged side by side along a first direction;
each shift register unit of the plurality of shift register units comprises an input circuit, an output circuit, a first reset circuit, and a frame reset signal connection line;
the frame reset signal connection line extends along a second direction and is configured to provide a frame reset signal to the first reset circuit, the second direction and the first direction cross each other;
the input circuit is configured to control a level of a first node in response to an input signal;
the output circuit is configured to receive a clock signal and output the clock signal as an output signal to an output terminal under control of the level of the first node;
the first reset circuit is configured to reset the first node and the output terminal in response to the frame reset signal;
the first reset circuit comprises a first transistor and a second transistor, and the frame reset signal connection line, a gate electrode of the first transistor, and a gate electrode of the second transistor are disposed in a first conductive layer;
the shift register unit further comprises a first transfer electrode in a second conductive layer, the gate electrode of the first transistor and the gate electrode of the second transistor are connected and both are electrically connected to the frame reset signal connection line through the first transfer electrode;
wherein a first electrode and a second electrode of the first transistor, and a first electrode and a second electrode of the second transistor are all disposed in the second conductive layer;
the gate electrode of the first transistor and the gate electrode of the second transistor are both connected to a first connection portion, the frame reset signal connection line includes a second connection portion, and the first transfer electrode includes a third connection portion and a forth connection portion, wherein an orthographic projection of the first connection portion on the base substrate and an orthographic projection of the third connection portion on the base substrate at least partially overlap, and an orthographic projection of the second connection portion on the base substrate and an orthographic projection of the forth connection portion on the base substrate at least partially overlap; and
the first connection portion disposed in the first conductive layer being electrically connected to the third connection portion disposed in the second conductive layer through a first via hole and a second via hole, and the second connection portion disposed in the first conductive layer being electrically connected to the forth connection portion disposed in the second conductive layer through a third via hole and a forth via hole.
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