| CPC G09G 3/3266 (2013.01) [G09G 3/22 (2013.01); G09G 2300/0413 (2013.01); G09G 2310/0264 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/028 (2013.01)] | 20 Claims |
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1. A gate driver comprising a plurality of stages, each of the plurality of stages comprising:
an eighth transistor connected between a third power input terminal and an output terminal, the eighth transistor including a gate electrode connected to a fourth node;
a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node;
an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node different from the third power input terminal;
a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal different from the third node; and
a third capacitor connected between the third power input terminal and the fourth node,
wherein a drain of the seventh transistor and a drain of the eighth transistors are connected to the output terminal forming a node with a gate line, a drain of the seventh transistor is connected to the second power input terminal, and a source of the eighth transistors is connected to the third power input terminal.
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